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80c575/83c575/87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer product specification supersedes data of 1998 jan 27 ic20 data handbook 1998 may 01 integrated circuits
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 2 1998 may 01 853-1684 19332 description the philips 80c575/83c575/87C575 is a high-performance microcontroller fabricated with philips high-density cmos technology. the philips cmos technology combines the high speed and density characteristics of hmos with the low power attributes of cmos. philips epitaxial substrate minimizes latch-up sensitivity. the 8xc575 contains an 8k 8 rom (83c575) eprom (87C575), a 256 8 ram, 32 i/o lines, three 16-bit counter/timers, a programmable counter array (pca), a seven-source, two-priority level nested interrupt structure, an enhanced uart, four analog comparators, power-fail detect and oscillator fail detect circuits, and on-chip oscillator and clock circuits. in addition, the 8xc575 has a low active reset, and the port pins are reset to a low level. there is also a fully configurable watchdog timer, and internal power on clear circuit. the part includes idle mode and power-down mode states for reduced power consumption. features ? 80c51 based architecture 8k 8 rom (83c575) 8k 8 eprom (87C575) romless (80c575) 256 8 ram three 16-bit counter/timers programmable counter array enhanced uart boolean processor oscillator fail detect low active reset asynchronous low port reset schmitt trigger inputs 4 analog comparators watchdog timer low v cc detect ? memory addressing capability 64k rom and 64k ram ? power control modes: idle mode power-down mode ? cmos and ttl compatible ? 4.0 to 16mhz ? extended temperature ranges ? otp package available pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 cmp0+/p1.0/t2 cmp0-/p1.1/t2ex eci/p1.2 cmp0/cex0/p1.3 cmp1/cex1/p1.4 cmp2/cex2/p1.5 cmp3/cex3/p1.6 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 cmpr-/t0/p3.4 cmp1+/t1/p3.5 cex4/p1.7 cmp2+/wr /p3.6 cmp3+/rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea /v pp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v dd pqfp 6 44 140 34 1 7 17 11 39 33 29 23 12 18 28 22 dual in-line package lcc su00234 ordering information romless rom eprom 1 temperature range c and package freq (mhz) drawing number p80c575ebp n p83c575ebp n p87C575ebpn otp 0 to +70, 40-pin plastic dual in-line package 16 sot129-1 p80c575eba a p83c575eba a p87C575ebaa otp 0 to +70, 44-pin plastic leaded chip carrier 16 sot187-2 p80c575ehaa p83c575ehaa p87C575ehaa otp 40 to +125, 44-pin plastic leaded chip carrier 16 sot187-2 p80c575ebb b p83c575ebb b p87C575ebbb otp 0 to +70, 44-pin plastic quad flat pack 16 sot307-2 note: 1. otp - one time programmable eprom.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 3 block diagram psen ea ale rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rom/ eprom register b acc tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr p1.0-p1.7 p3.0-p3.7 p0.0-p0.7 p2.0-p2.7 stack pointer sfrs timers pca su00238
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 4 ceramic and plastic leaded chip carrier pin functions lcc 6140 7 17 39 29 18 28 pin function 1 nc* 2 t2/p1.0/cmp0+ 3 t2ex/p1.1/cmp0 4 p1.2/eci 5 p1.3/cmp0/cex0 6 p1.4/cmp1/cex1 7 p1.5/cmp2/cex2 8 p1.6/cmp3/cex3 9 p1.7/cex4 10 rst 11 rxd/p3.0 12 nc* 13 txd/p3.1 14 int 0/p3.2 15 int 1/p3.3 16 t0/p3.4/cmpr 17 t1/p3.5/cmp1+ 18 wr /p3.6/cmp2+ 19 rd /p3.7/cmp3+ 20 xtal2 21 xtal1 22 v ss pin function 23 nc* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 31 p2.7/a15 32 psen 33 ale/prog 34 nc* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su00235 * no internal connection plastic quad flat pack pin functions pqfp 44 34 1 11 33 23 12 22 su00236 pin function 1 p1.5/cmp2/cex2 2 p1.6/cmp3/cex3 3 p1.7/cex4 4 rst 5 rxd/p3.0 6 nc* 7 txd/p3.1 8 int 0/p3.2 9 int 1/p3.3 10 t0/p3.4/cmpr 11 t1/p3.5/cmp1+ 12 wr /p3.6/cmp2+ 13 rd /p3.7cmp3+ 14 xtal2 15 xtal1 16 v ss 17 nc* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 pin function 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale/prog 28 nc* 29 ea /v pp 30 p0.7/ad7 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nc* 40 t2/p1.0/cmp0+ 41 t2ex/p1.1/cmp0 42 p1.2/eci 43 p1.3/cmp0/cex0 44 p1.4/cmp1/cex1 * no internal connection logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 cmpr cmp1+ cmp2+ cmp3+ cmp0+ cmp0 eci cmp0/cex0 cmp1/cex1 cmp2/cex2 cmp3/cex3 cex4 su00237
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 5 pin descriptions pin number mnemonic dip lcc qfp type name and function v ss 20 22 16 i ground: 0v reference. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.0-0.7 39-32 43-36 37-30 i/o port 0: port 0 is an open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 0 also receives code bytes during eprom programming and outputs code bytes during program verification. external pull-ups are required during program verification. during reset, port 0 will be asynchronously driven low and will remain low until written to by software. all port 0 pins have schmitt trigger inputs with 200mv hysteresis. a weak pulldown on port 0 guarantees positive leakage current (see dc electrical characteristics: i l1 ). p1.0-p1.7 1-8 2-9 40-44 1-3 i/o port 1: port 1 is an 8-bit bidirectional i/o port. port 1 pins have internal pull-ups such that pins that have 1s written to them can be used as inputs but will source current when externally pulled low (see dc electrical characteristics: i il ). port 1 receives the low-order address byte during program memory verification and eprom programming. during reset, port 1 will be asynchronously driven low and will remain low until written to by software. all port 1 pins have schmitt trigger inputs with 50mv hysteresis. port 1 pins also serve alternate functions as follows: 1 2 40 i/o p1.0 t2 timer 2 external i/o clockout (programmable) cmp0+ comparator 0 positive input 2 3 41 i p1.1 t2ex timer 2 capture input cmp0- comparator 0 negative input 3 4 42 i p1.2 eci pca count input 4 5 43 i/o p1.3 cex0 pca module 0 external i/o cmp0 comparator 0 output 5 6 44 i/o p1.4 cex1 pca module 1 external i/o cmp1 comparator 1 output 6 7 1 i/o p1.5 cex2 pca module 2 external i/o cmp2 comparator 2 output 7 8 2 i/o p1.6 cex3 pca module 3 external i/o cmp3 comparator 3 output 8 9 3 i/o p1.7 cex4 pca module 4 external i/o p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them can be used as inputs, but will source current when externally pulled low (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during accesses to external program and data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. port 2 receives the high-order address byte during program verification and eprom programming. during reset, port 2 will be asynchronously driven low and will remain low until written to by software. port 2 can be made open drain by writing to the p2od register (aih). in open drain mode, weak pulldowns on port 2 guarantee positive leakage current (see dc electrical characteristics i l1 ). p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins except p3.1 that have 1s written to them can be used as inputs but will source current when externally pulled low (see dc electrical characteristics: i il ). p3.1 will be a high impedance pin except while transmitting serial data, in which case the strong pull-up will remain on continuously when outputting a 1 level. the p3.1 output drive level when transmitting can be set to one of two levels by the writing to the p3.1 register bit. during reset all pins (except p3.1) will be asynchronously driven low and will remain low until written to by software. all port 3 pins have schmitt trigger inputs with 200mv hysteresis, except p3.2 and p3.3, which have 50mv hysteresis. port 3 pins serve alternate functions as follows:
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 6 pin descriptions (continued) pin number mnemonic dip lcc qfp type name and function port 3: (continued) 10 11 5 i p3.0 rxd serial receive port 11 13 7 o p3.1 txd serial transmit port enabled only when transmitting serial data 12 14 8 i p3.2 int0 external interrupt 0 13 15 9 i p3.3 int1 external interrupt 1 14 16 10 i p3.4 t0 timer/counter 0 input cmpr- common - reference to comparators 1, 2, 3 15 17 11 i p3.5 t1 timer/counter 1 input cmp1+ comparator 1 positive input 16 18 12 o p3.6 wr external data memory write strobe cmp2+ comparator 2 positive input 17 19 13 o p3.7 rd external data memory read strobe cmp3+ comparator 3 positive input rst 9 10 4 i reset: a low on this pin asynchronously resets all port pins to a low state except p3.1. the pin must be held low with the oscillator running for 24 oscillator cycles to initialize the internal registers. an internal diffused resistor to v cc permits a power on reset using only an external capacitor to v ss . rst has a schmitt trigger input stage to provide additional noise immunity with a slow rising input voltage. ale/prog 30 33 27 i/o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale is switched off if the bit 0 in the auxr register (8eh) is set. this pin is also the program pulse input (prog ) during eprom programming. psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 31 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 1fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 1fffh. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 7 table 1. 87C575 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh lo ao xxxxxx00b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccap0h# module 0 capture high fah xxxxxxxxb ccap1h# module 1 capture high fbh xxxxxxxxb ccap2h# module 2 capture high fch xxxxxxxxb ccap3h# module 3 capture high fdh xxxxxxxxb ccap4h# module 4 capture high feh xxxxxxxxb ccap0l# module 0 capture low eah xxxxxxxxb ccap1l# module 1 capture low ebh xxxxxxxxb ccap2l# module 2 capture low ech xxxxxxxxb ccap3l# module 3 capture low edh xxxxxxxxb ccap4l# module 4 capture low eeh xxxxxxxxb ccapm0# module 0 mode dah ecom capp capn mat tog pwm eccf x0000000b ccapm1# module 1 mode dbh ecom capp capn mat tog pwm eccf x0000000b ccapm2# module 2 mode dch ecom capp capn mat tog pwm eccf x0000000b ccapm3# module 3 mode ddh ecom capp capn mat tog pwm eccf x0000000b ccapm4# module 4 mode deh ecom capp capn mat tog pwm eccf x0000000b df de dd dc db da d9 d8 ccon*# pca counter control d8h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b ch# pca counter high f9h 00h cl# pca counter low e9h 00h cmod# pca counter mode d9h cidl wdte cps1 cps0 ecf 00xxx000b ef ee ed ec eb ea e9 e8 cmp*# comparator e8h ec3dp ec2dp ec1dp ec0dp c3ro c2ro c1ro c0ro 00h cmpe# comparator enable 91h ec3tdc ec2tdc ec1tdc ec0tdc ec3od ec2od ec1od ec0od 00h dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie* interrupt enable a8h ea ec et2 es et1 ex1 et0 ex0 00h bf be bd bc bb ba b9 b8 ip* interrupt priority b8h ppc pt2 ps pt1 px1 pt0 px0 x0000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 00h 97 96 95 94 93 92 91 90 p1* port 1 90h cex4 cex3 cex2 cex1 cex0 exi t2ex t2 00h a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 00h b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. 87C575 only.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 8 table 1. 87C575 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value p2od# port 2 pullup disable a1h 00h pcon# power control 87h smod1 smod0 osf 1 pof 1 lvf 1 gf0 pd idl 00xxx000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h racap2h# timer 2 capture high cbh 00h racap2l # timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00h t2mod# timer 2 mode control c9h t2oe 2 dcen xxxxxxx0b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h c7 c6 c5 c4 c3 c2 c1 c0 wdcon *# watchdog timer control c0h pre2 pre1 pre0 lvre ofre wdrun wdtof wdmod 11111 101b wdl# watchdog timer reload c1h 00h wfeed1# watchdog feed 1 c2h xxh wfeed2# watchdog feed 2 c3h xxh * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. reset value depends on reset source. 2. programmable clock-out.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 9 power on clear/ power on flag an on-chip power on detect circuit resets the 8xc575 and sets the power off flag (pcon.4) on power up or if v cc drops to zero momentarily. the pof can only be cleared by software. the rst pin is not driven by the power on detect circuit. the pof can be read by software to determine that a power failure has occurred and can also be set by software. low voltage detect an on-chip low voltage detect circuit sets the low voltage flag (pcon.3) if v cc drops below v low (see dc electrical characteristics) and resets the 8xc575 if the low voltage reset enable bit (wdcon.4) is set. if the lvre is cleared, the reset is disabled but lvf will still be set if v cc is low. the rst pin is not driven by the low voltage detect circuit. the lvf can be read by software to determine that v cc was low. the lvf can be set or cleared by software. oscillator fail detect an on-chip oscillator fail detect circuit sets the oscillator fail flag (pcon.5) if the oscillator frequency drops below oscf for one or more cycles (see ac electrical characteristics: oscf) and resets the 8xc575 if the oscillator fail reset enable bit (wdcon.3) is set. if ofre is cleared, the reset is disabled but osf will still be set if the oscillator fails. the rst pin is not driven by the oscillator fail detect circuit. the osf can be read by software to determine that an oscillator failure has occurred. the osf can be set or cleared by software. low active reset one of the most notable features on this part is the low active reset. at this time this is the only 80c51 derivative available that has low active reset. this feature makes it easier to interface the 8xc575 into an application to accommodate the power-on and low voltage conditions that can occur. the low active reset operates exactly the same as high active reset with the exception that the part is put into the reset mode by applying a low level to the reset pin. for power-on reset it is also necessary to invert the power-on reset circuit; connecting the 8.2k resistor from the reset pin to v cc and the 10 m f capacitor from the reset pin to ground. figure 1 shows all of the reset related circuitry. when reset the port pins on the 87C575 are driven low asynchronously. this is different from all other 80c51 derivatives. the 8xc575 also has low voltage detection circuitry that will, if enabled, force the part to reset when v cc (on the part) fails below a set level. low voltage reset is enabled by a normal reset. low voltage reset can be disabled by clearing lvre (bit 4 in the wdcon sfr) then executing a watchdog feed sequence (a5h to wfeed1 followed immediately by 5a to wfeed2). in addition there is a flag (lvf) that is set if a low voltage condition is detected. the lvf flag is set even if the low voltage detection circuitry is disabled. notice that the low voltage detection circuitry does not drive the rst# pin so the lvf flag is the only way that the microcontroller can determine if it has been reset due to a low voltage condition. the 8xc575 has an on-chip power-on detection circuit that sets the pof (pcon.4) flag on power up or if the v cc level momentarily drops to 0v. this flag can be used to determine if the part is being started from a power-on (cold start) or if a reset has occurred due to another condition (warm start). timers the 87C575 has four on-chip timers. timers 0 and 1 are identical in every way to timers 0 and 1 on the 80c51. timer 2 on the 8xc575 is identical to the 80c52 timer 2 (described in detail in the 80c52 overview) with the exception that it is an up or down counter. to configure the timer to count down the dcen bit in the t2mod special function register must be set and a low level must be present on the t2ex pin (p1.1). the watchdog timer operation and implementation is the same as that for the 8xc550 (described in the 8xc550 overview) with the exception that the reset values of the wdcon and wdl special function registers have been changed. the changes in these registers cause the watchdog timer to be enabled with a timeout of 98304 t osc when the part is reset. the watchdog can be disabled by executing a valid feed sequence and then clearing wdrun (bit 2 in the wdcon sfr). pre2 pre1 pre0 lvre ofre wdrun wdtof wdmod wdcon (c0h) shadow register for wdcon watchdog feed smod1 smod0 osf lvf gf0 gf1 idl pcon (87gh) osc freq below oscf (min frequency) rst + v cc vlow (low v cc reference) power-on detect pca watchdog watchdog timer 8xc575 internal reset pof su00239 figure 1. reset circuitry
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 10 programmable counter array (pca) the programmable counter array is a special timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p1.3(cex0), module 1 to p1.4(cex1), etc.. the basic pca configuration is shown in figure 2. the pca timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p1.2). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 3): cps1 cps0 pca timer count source 0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 timer 0 overflow 1 1 external input at eci pin in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 3. the watchdog timer function is implemented in module 4 as implemented in other parts that have a pca that are available on the market. however, if a watchdog timer is required in the target application, it is recommended to use the hardware watchdog timer that is implemented on the 87C575 separately from the pca (see figure 14). the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to figure 6). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the pca interrupt system shown in figure 4. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 7). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. figure 8 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. refer to figure 9. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 10). high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 11). module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p1.3/cex0 p1.4/cex1 p1.5/cex2 p1.6/cex3 p1.7/cex4 16 bits pca timer/counter time base for pca modules 16 bits su00032 figure 2. programmable counter array (pca)
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 11 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (d9h) cidl wdte cps1 cps0 ecf osc/12 osc/4 timer 0 overflow external input (p1.2/eci) decode 00 01 10 11 su00033 figure 3. pca timer/counter module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf ccapmn.0 eccfn to interrupt priority decoder ccon (d8h) ie.6 ec ie.7 ea su00034 figure 4. pca interrupt system
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 12 cmod address = od9h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc 12 0 1 1 internal clock, f osc 4 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p1.2 pin (max. rate = f osc 8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su00035 76543210 figure 5. cmod: pca counter mode register ccon address = od8h reset value = 00x0 0000b cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00036 76543210 figure 6. ccon: pca counter control register
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 13 ccapmn address ccapm0 0dah ccapm1 0dbh ccapm2 0dch ccapm3 0ddh ccapm4 0deh reset value = x000 0000b ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00037 76543210 figure 7. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 8. pca module modes (ccapmn register)
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 14 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su00749 figure 9. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su00750 figure 10. pca compare mode
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 15 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su00751 figure 11. pca high speed output mode pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 12 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. watchdog timer the watchdog timer is not directly loadable by the user. instead, the value to be loaded into the main timer is held in an autoload register or is part of the mask rom programming. in order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. this operation is referred to as feeding the watchdog timer. to feed the watchdog, two instructions must be sequentially executed successfully. no intervening instruction fetches are allowed, so interrupts should be disabled before feeding the watchdog. the instructions should move a5h to the wfeed1 register and then 5ah to the wfeed2 register. if wfeed1 is correctly loaded and wfeed2 is not correctly loaded, then an immediate underflow will occur. the watchdog timer subsystem has two modes of operation. its principal function is a watchdog timer. in this mode it protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. if the user does not employ the watchdog function, the watchdog subsystem can be used as a timer. in this mode, reaching the terminal count sets a flag. in most other respects, the timer mode possesses the characteristics of the watchdog mode. this is done to protect the integrity of the watchdog function. the watchdog timer subsystem consists of a prescaler and a main counter. the prescaler has 8 selectable taps off the final stages and the output of a selected tap provides the clock to the main counter. the main counter is the section that is loaded as a result of the software feeding the watchdog and it is the section that causes the system reset (watchdog mode) or time-out flag to be set (timer mode) if allowed to reach its terminal count. programming the watchdog timer both the eprom and rom devices have a set of sfrs for holding the watchdog autoload values and the control bits. the watchdog time-out flag is present in the watchdog control register and operates the same in all versions. in the eprom device, the watchdog parameters (autoload value and control) are always taken from the sfrs. in the rom device, the watchdog parameters can be mask programmed or taken from the sfrs. the selection to take the watchdog parameters from the sfrs or from the mask programmed values is controlled by ea (external access). when ea is high (internal rom access), the watchdog parameters are taken from the mask programmed values. if the watchdog is mask programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the sfrs. when ea is low (external access), the watchdog parameters are taken from the sfrs. the user should be able to leave code in his program which initializes the watchdog sfrs even though he has migrated to the mask rom part. this allows no code changes from eprom prototyping to rom coded production parts.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 16 cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su00752 figure 12. pca pwm mode watchdog detailed operation eprom device (and romless operation: ea = 0) in the romless operation (rom part, ea = 0) and in the eprom device, the watchdog operates in the following manner (see figure 14). whether the watchdog is in the watchdog or timer mode, when external reset is applied, the following takes place: ? watchdog mode bit set to watchdog mode. ? watchdog run control bit set to on. ? autoload register set to 00 (min. count). ? watchdog time-out flag cleared. ? prescaler is cleared. ? prescaler tap set to the highest divide. ? autoload takes place. the watchdog can be fed even though it is in the timer mode. note that the operational concept is for the watchdog mode of operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, and then feed the watchdog (cause an autoload). the watchdog will now be starting at a known point. if the watchdog is in the watchdog mode and running and happens to underflow at the time the external reset is applied, the watchdog time-out flag will be cleared. when the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place (see figure 16): ? autoload takes place. ? watchdog time-out flag is set ? mode bit unchanged. ? watchdog run bit unchanged. ? autoload register unchanged. ? prescaler tap unchanged. ? all other device action same as external reset. note that if the watchdog underflows, the program counter will start from 00h as in the case of an external reset. the watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. the watchdog time-out flag bit can be cleared by software. when the watchdog is in the timer mode and the timer software underflows, the following action takes place: ? autoload takes place. ? watchdog time-out flag is set ? mode bit unchanged. ? watchdog run bit unchanged. ? autoload register unchanged. ? prescaler tap unchanged. mask rom device (ea = 1) in the mask rom device, the watchdog mode bit (wdmod) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. if the mask programmed mode bit selects the timer mode, then the watchdog run bit (wdrun) operates as described under eprom device. if the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation (see figure 15). watchdog function the watchdog consists of a programmable prescaler and the main timer. the prescaler derives its clock from the on-chip oscillator. the prescaler consists of a divide by 12 followed by a 13 stage counter with taps from stage 6 through stage 13. this is shown in figure 17. the tap selection is programmable. the watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler underflows. the watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the clock to decrement the watchdog occurs. the watchdog is 8 bits long and the autoload value can range from 0 to ffh. (the autoload value of 0 is permissible since the prescaler is cleared upon autoload). this leads to the following user design equations. definitions :t osc is the oscillator
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 17 period, n is the selected prescaler tap value, w is the main counter autoload value, t min is the minimum watchdog time-out value (when the autoload value is 0), t max is the maximum time-out value (when the autoload value is ffh), t d is the design time-out value. t min = t osc 12 64 t max = t min 128 256 t d = t min 2 prescaler (w + 1) (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7) note that the design procedure is anticipated to be as follows. a t max will be chosen either from equipment or operation considerations and will most likely be the next convenient value higher than t d . (if the watchdog were inadvertently to start from ffh, an overflow would be guaranteed, barring other anomalies, to occur within t max ). then the value for the prescaler would be chosen from: prescaler = log2 (t max / (t osc 12 256)) - 6 this then also fixes t min . an autoload value would then be chosen from: w = t d / t min - 1 the software must be written so that a feed operation takes place every t d seconds from the last feed operation. some tradeoffs may need to be made. it is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. watchdog control register (wdcon) (bit addressable) address c0 the following bits of this register are read only in the rom part when ea is high: wdmod, pre0, pre1, and pre2. that is, the register will reflect the mask programmed values. in the rom part with ea high, these bits are taken from mask coded bits and are not readable by the program. wdrun is read only in the rom part when ea is high and wdmod is in the watchdog mode. when wdmod is in the timer mode, wdrun functions normally. the parameters written into wdmod, pre0, pre1, and pre2 by the program are not applied directly to the watchdog timer subsystem. the watchdog timer subsystem is directly controlled by a second register which stores these bits. the transfer of these bits from the user register (wdmod) to the second control register takes place when the watchdog is fed. this prevents random code execution from directly foiling the watchdog function. this does not affect the operation where these bits are taken from mask coded values. the reset values of the wdcon and wdl registers will be such that the timer resets to the watchdog mode with a timeout period of 12 64 128 t osc . the watchdog timer will not generate an interrupt. additional bits in wdcon are used to disable reset generation by the oscillator fail and low voltage detect circuits. wdcon can be written by software only by executing a valid watchdog feed sequence. wdcon register bit definitions wdcon.7 pre2 prescaler select 2, reset to 1 wdcon.6 pre1 prescaler select 1, reset to 1 wdcon.5 pre0 prescaler select 0, reset to 1 wdcon.4 lvre low voltage reset enable, reset to 1 (enabled) wdcon.3 ofre oscillator fail reset enable, reset to 1 (enabled) wdcon.2 wdrun watchdog run, reset to 1 (enabled) wdcon.1 wdtof watchdog timeout flag, reset = indeterminate wdcon.0 wdmod watchdog mode, reset to 1 (watchdog mode) enhanced uart the uart operates in all of the usual modes that are described in the first section of this book for the 80c51. in addition the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the 87C575 uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 19). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 18. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 20. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 18 ecomn cappn capnn matn togn pwmn eccfn ccapm4 (deh) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4h reset write to ccap4l 01 1 cmod (d9h) cidl wdte cps1 cps0 ecf x su00042 figure 13. pca watchdog timer pre2 pre1 pre0 lvre ofre wdrun wdtof wdmod wdcon (c0h) reset 8bit down counter prescaler osc/12 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence shadow register for wdcon wdl (c1h) su00240 figure 14. watchdog timer in 87C575 and 80c575 / 83c575 (ea = 0)
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 19 pre2 pre1 pre0 lvre ofre wdrun wdtof wdmod wdcon (c0h) 8bit down counter prescaler osc/12 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence shadow register for wdcon romcode content wd pre2:0 wdmod address 2032h 2031h 2030h 1 su00241 figure 15. watchdog timer of 83c575 in watchdog mode (ea = 1, wdmod = 1) pre2 pre1 pre0 lvre ofre wdrun wdtof wdmod wdcon (c0h) 8bit down counter prescaler osc/12 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence shadow register for wdcon romcode content wd pre2:0 wdmod address 2032h 2031h 2030h 0 su00242 figure 16. watchdog timer of 83c575 in timer mode (ea = 1, wdmod = 0)
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 20 2 2 2 2 2 2 2 pre2 pre1 pre0 000 001 010 011 100 101 110 111 osc/12 64 64 128 256 512 1024 2048 4096 8192 to watchdog down counter decode su00243 figure 17. watchdog prescaler scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0 is located at pcon6. **f osc = oscillator frequency su00043 bit: 76543210 figure 18. scon: serial port control register
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 21 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su00044 figure 19. uart framing error detection using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to b used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are loaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature. analog comparators four analog comparators are provided on chip. three comparators have a common negative reference cmpr- and independent positive inputs cmp1+, cmp2+, cmp3+ on port 3. the fourth comparator has independent positive and negative inputs cmp0+ and cmp0- on port 1. the cmp register contains an output and enable bit for each comparator. the cmp register is bit addressable and is located at sfr address e8h. figure 21 shows the connection of the comparators. pullups at the comparator input pins will be disabled by hardware when the comparator is enabled. in addition, to make inputs high impedance, the corresponding port sfr bits must be set by software to disable the pulldowns.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 22 sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 20. uart multiprocessor communication, automatic address recognition cmp register bit definitions cmp.7 enable comparator 3, disable pullups at p3.4, p3.7 cmp.6 enable comparator 2, disable pullups at p3.4, p3.6 cmp.5 enable comparator 1, disable pullups at p3.4, p3.5 cmp.4 enable comparator 0, disable pullups at p1.0, p1.1 cmp.3 comparator 3 output (read only) cmp.2 comparator 2 output (read only) cmp.1 comparator 1 output (read only) cmp.0 comparator 0 output (read only) all comparators are disabled automatically in power down mode, in idle mode unused comparators should be disabled by software to save power. a comparator can generate an interrupt that will terminate idle mode. the cmpe register contains bits to enable each comparator to drive external output pins or internal pca capture inputs. pullups at the output pins are disabled by hardware when the external comparator output is enabled. the comparator output is wire-ored with the corresponding port sfr bit, so the sfr bit must also be set by software to enable the output. cmpe register bit definitions cmpe.7 enables comparator 3 to drive cex3 cmpe.6 enables comparator 2 to drive cex2 cmpe.5 enables comparator 1 to drive cex1 cmpe.4 enables comparator 0 to drive cex0 cmpe.3 enables comparator 3 output on p1.6 (open drain) cmpe.2 enables comparator 2 output on p1.5 (open drain) cmpe.1 enables comparator 1 output on p1.4 (open drain) cmpe.0 enables comparator 0 output on p1.3 (open drain) when 1s are written to cmpe bits 7-4, the comparator outputs will drive the corresponding capture input. (this function is not available in the idle or power-down mode.) when 1s are written to cmpe bits 3-0 the comparator output will also drive the corresponding port 1 pin. (this function is available in idle mode.) if the comparator's enabled to drive the capture input but not the port pin, then the port pin can be used for general purpose i/o. when a comparator output is enabled, pullups at the output pin are disabled and the output becomes open drain. the comparator output can be used to trigger a capture input in idle mode by programming the cmpe register to drive the pin from the comparator output to have the pin supply the capture trigger. there are two special function registers associated with the comparators. they are cmp which contains the comparator enables and a bit that can be read by software to determine the state of each comparator's output, and cmpe which controls whether the output from each comparator drives the associated output pin or a capture input associated with one of the pca modules. the cmp registers bits 03 can be read by software to determine the state of the output of each comparator. to do this the associated comparator must be enabled but the output in port 1 can be disabled. this allows easy polling of the comparator output value without the need to use up a port pin. the cmpe register allows the comparator to drive the associated pca module capture input, so that on compare a capture can be generated in the pca. bits 03 of this register enable the comparator output to drive the associated port 1 output circuitry. used as a comparator output this circuitry is open drain. to enable the comparator output to drive to port 1, the corresponding port bit must also be set to disable the pulldown. if the comparator is not enabled to drive the port 1 circuitry, the associated port 1 pin can be used for other i/o. this includes when a comparator is enabled to drive the capture input to a pca module.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 23 + + + + * : will disable pullups on relevant pins p3.5 / cmp1+ p3.6 / cmp2+ p3.7 / cmp3+ p3.4 / cmpr p1.0 / cmp0+ p1.1 / cmp0 ec3dp * ec2dp * ec1dp * ec0dp * c3r0 c2r0 c1r0 c0r0 cmp (e8h) ec3tdc ec2tdc ec1tdc ec0tdc ec3od * ec2od * ec1od * ec0od * cmpe (91h) p1.3 / cmp0 p1.4 / cmp1 p1.5 / cmp2 p1.6 / cmp3 enable enable enable enable to cex0 input of pca module 0 to cex1 input of pca module 1 to cex2 input of pca module 2 to cex3 input of pca module 3 su00244 figure 21. analog comparators reduced emi mode there are two bits in the auxr register that can be set to reduce the internal clock drive and disable the ale output. ao (auxr.0) when set turns off the ale output. lo (auxr.1) when set reduces the drive of the internal clock circuitry. both bits are cleared on reset. with lo set the 87C575 will still operate at 12mhz, but will have reduced emi in the range above 100mhz. auxr (8eh) lo ao ao: turns off ale output. lo: reduces drive of internal clock circuitry. 8xc575 spec'd to 12mhz when lo set. internal reset internal resets generated by the power on, low voltage, and oscillator fail detect circuits are self timed to guarantee proper initialization of the 8xc575. reset will be held approximately 24 oscillator periods after normal conditions are detected by all enabled detect circuits. internal resets do not drive rst but will cause missing pulses on ale. interrupt enable (ie) register ea ie.7 enable all interrupts ec ie.6 enable pca interrupt et2 ie.5 enable timer 2 interrupt es ie.4 enable serial i/o interrupt et1 ie.3 enable timer 1 interrupt ex1 ie.2 enable external interrupt 1 et0 ie.1 enable timer 0 interrupt ex0 ie.0 enable external interrupt 0 interrupt priority (ip) register ip.7 reserved ppc ip.6 pca interrupt priority pt2 ip.5 timer 2 interrupt priority ps ip.4 serial i/o interrupt priority pt1 ip.3 timer 1 interrupt priority px1 ip.2 external interrupt 1 priority pt0 ip.1 timer 0 interrupt priority px0 ip.0 external interrupt 0 priority priority source flag vector 1 int0 ie0 03h highest priority 2 timer 0 tf0 0bh 3 int1 ie1 13h 4 timer 1 tf1 1bh 87C575 5 pca cf,ccfn 33h 6 serial i/o ri,ti 23h 7 timer 2 tf2/exf2 2bh lowest priority 80c575/83c575/87C575 5 serial i/o ri/ti 23h 6 timer 2 tf2/exf2 23h 7 pca cf, ccf n 33h lowest priority power control (pcon) register smod1 pcon.7 double baud rate bit smod0 pcon.6 scon.7 access control osf pcon.5 oscillator fail flag pof pcon.4 power off flag lvf pcon.3 low voltage flag gf0 pcon.2 general purpose flag pd pcon.1 power down mode bit idl pcon.0 idle mode bit port 2 pullup disable register
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 24 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 4. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. the control bits for the reduced power modes are in the special function register pcon. power-down mode can be terminated with either a hardware reset or external interrupt. with an external interrupt int0 or int1 must be enabled and configured as level sensitive. holding the pin low restarts to oscillator and bringing the pin back high completes the exit. if the watchdog is enabled (wdrun = 1), then power-down mode is disabled. design considerations at power-on, the voltage on v cc must come up with rst low for a proper start-up. table 2 shows the state of i/o ports during low current operating modes. table 2. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 25 rom code submission when submitting rom code for the 83c575, the following must be specified: 1. 8k byte user rom data 2. 32 byte rom encryption key 3. rom security bits 4. the watchdog timer parameters. address content bit(s) comment 0000h to 1fffh data 7:0 user rom data 2000h to 201fh key 7:0 rom encryption key ffh = no encryption 2020h reserved security bit 2 security bit 1 2 1 0 must = 1 0 = enable, 1 = disable 0 = enable, 1 = disable 2030h reserved 7:0 must = ffh 2031h reserved 7:0 must = ffh 2032h wdl 1 7:0 watchdog reload value (see specification) 2033h wdcon 1 7:5 pre2:0 2033h wdcon 1 4 lvre 2033h wdcon 1 3 ofre 2033h wdcon 1 2 wdrun=0, not rom coded 2033h wdcon 1 1 wdtof=0, not rom coded 2033h wdcon 1 0 wdmod notes: 1. see watchdog timer specification for definition of wdl and wdcon bits. security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea# is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 26 dc electrical characteristics t amb = 0 c to +70 c and 40 c to +125 c, v cc = 5v 10%, v ss = 0v symbol parameter test limits unit symbol parameter conditions min typ 1 max unit v il input low voltage (ports 0, 2, 3, except 3.2, 3.3) 0.5 0.5v cc 0.6 v v il1 input low voltage (ports 1, 3.2, 3.3, xtal1, rst) 0.5 0.2v cc 0.5 v v il2 input low voltage (ea ) 0 0.2v cc 0.45 v v ih input high voltage (ports 0, 2, 3, except 3.2, 3.3) 0.5v cc +0.8 v cc +0.5 v v ih1 input high voltage (ports 1, 3.2, 3.3) 0.8v cc +0.3 v cc +0.5 v v ih2 input high voltage (ea ) 0.2v cc +0.9 v cc +0.5 v v ih3 input high voltage (xtal1, rst) 0.7v cc v cc +0.5 v hys hysteresis (ports 0, 2, 3, except 3.2, 3.3) 200 mv hys1 hysteresis (ports 1, 3.2, 3.3) 50 mv v ol output voltage low (ports 1, 2, 3, except 3.1) i ol = 1.6ma 0.45 v v ol1 output voltage low (ports 0, ale, psen ) i ol = 3.2ma 0.45 v v ol2 output voltage low p3.1 with bit cleared p3.1 with bit set i ol = 10.0ma i ol = 1.6ma 0.50 0.45 v v v oh output voltage high (ports 1, 2, 3, except p3.1) i oh = 30 m a v cc 0.7 v v oh1 output voltage high (port 0 in external bus mode, ale, psen ) i oh = 3.2ma v cc 0.7 v v oh2 output voltage high p3.1 with bit cleared p3.1 with bit set i oh = 10.0ma i oh = 1.6ma v cc 1.5 v cc 1.5 v v v io offset voltage comparator inputs 35 +35 mv v cr common mode range comparator inputs 0 v cc v i il logical 0 input current (ports 1, 2, 3, except 3.1) v in = 0.45v 75 m a i tl logical 1-to-0 transition current (ports 2, 3, except 3.1, 3.2, 3.3) 4 see note 4 600 m a i tl1 logical 1-to-0 transition current (ports 1, 3.2, 3.3) see note 4 450 m a i l1 input leakage current (port 0, port2 in open drain mode) 9 0.45 < v in < v cc 2 40 m a i l2 input leakage current (ea , p3.1) 0.45 < v in < v cc 10 +10 m a i lc input leakage current comparator inputs 0 < v in < v cc 1.0 +1.0 m a i cc power supply current: 7 active mode @ 16mhz 5 idle mode @ 16mhz power-down mode see note 6 20 8 5 30 12 75 ma ma m a r rst internal reset pull-up resistor v in = 0v 50 200 k w v low low v cc detect voltage 4.0 4.45 v c io pin capacitance 10 f = 1mhz 10 pf notes: (see next page)
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 27 notes to the dc electrical characteristics table: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is between v ih and v il . 5. i cc max at other frequencies can be determined from figure 29. 6. see figures 30 through 33 for i cc test conditions. 7. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. specification applies to port 2 when p2od bit is set. 10. 15pf max for the ea /v pp and p0.0 pins.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 28 ac electrical characteristics t amb = 0 c to +70 c and 40 c to +125 c, v cc = 5v 10%, v ss = 0v 1, 2 variable clock symbol figure parameter min max unit 1/t clcl 22 oscillator frequency: speed versions 8xc575 e 6 16 mhz oscf oscillator fail detect frequency 0.6 5.5 mhz tr comparator response time 10 m s t lhll 22 ale pulse width 2t clcl 40 ns t avll 22 address valid to ale low t clcl 25 ns t llax 22 address hold after ale low t clcl 25 ns t lliv 22 ale low to valid instruction in 4t clcl 75 ns t llpl 22 ale low to psen low t clcl 25 ns t plph 22 psen pulse width 3t clcl 45 ns t pliv 22 psen low to valid instruction in 3t clcl 70 ns t pxix 22 input instruction hold after psen 0 ns t pxiz 22 input instruction float after psen t clcl 25 ns t aviv 22 address to valid instruction in 5t clcl 85 ns t plaz 22 psen low to address float 10 ns data memory t rlrh 23, 24 rd pulse width 6t clcl 100 ns t wlwh 23, 24 wr pulse width 6t clcl 100 ns t rldv 23, 24 rd low to valid data in 5t clcl 110 ns t rhdx 23, 24 data hold after rd 0 ns t rhdz 23, 24 data float after rd 2t clcl 28 ns t lldv 23, 24 ale low to valid data in 8t clcl 150 ns t avdv 23, 24 address to valid data in 9t clcl 165 ns t llwl 23, 24 ale low to rd or wr low 3t clcl 50 3t clcl +50 ns t avwl 23, 24 address valid to wr low or rd low 4t clcl 75 ns t qvwx 23, 24 data valid to wr transition t clcl 30 ns t whqx 23, 24 data hold after wr t clcl 25 ns t rlaz 23, 24 rd low to address float 0 ns t whlh 23, 24 rd or wr high to ale high t clcl 25 t clcl +25 ns external clock t chcx 26 high time 12 ns t clcx 26 low time 12 ns t clch 26 rise time 20 ns t chcl 26 fall time 20 ns shift register t xlxl 25 serial port clock cycle time 12t clcl ns t qvxh 25 output data setup to clock rising edge 10t clcl 133 ns t xhqx 25 output data hold after clock rising edge 2t clcl 60 ns t xhdx 25 input data hold after clock rising edge 0 ns t xhdv 25 clock rising edge to input data valid 10t clcl 133 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 3. interfacing the 80c32/52 to devices with float times up to 45ns is permitted. this limited bus contention will not cause dama ge to port 0 drivers.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 29 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl =time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 22. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 23. external data memory read cycle
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 30 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 24. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 figure 25. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 26. external clock drive
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 31 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00010 figure 27. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 28. float waveform frequency (mhz) max active typ active max idle typ idle i cc (ma) 045 10 151620 30 25 20 15 10 5 0 su00245 figure 29. i cc vs. freq valid only within frequency specifications of the device under test
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 32 v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00246 figure 30. i cc test condition, active mode all other pins are disconnected v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00247 figure 31. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 32. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 33 v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00248 figure 33. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 34 eprom characteristics to put the 87C575 in the eprom programming mode, psen must be held high during power up, then driven low with reset active. the 87C575 is programmed by using a modified quick-pulse programming ? algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the 87C575 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an 87C575 manufactured by philips. table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 34 and 35. figure 36 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 34. note that the 87C575 is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 34. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 2 and 3 specified in table 3 are held at the `program code data' levels indicated in table 3. the ale/prog is pulsed low 25 times as shown in figure 35. to program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 25 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 1 and 2 as shown in figure 36. the other pins are held at the `verify code data' levels indicated in table 3. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low. the values are: (030h) = 15h indicates manufactured by philips (b0h) = 97h indicates 87C575 program/verify algorithms any algorithm in agreement with the conditions listed in table 3, and which satisfies the timing specifications, is suitable. table 3. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p3.7 p3.6 read signature 0 0 1 1 0 0 0 0 program code data 0 0 0* v pp 1 0 1 1 verify code data 0 0 1 1 0 0 1 1 pgm encryption table 0 0 0* v pp 1 0 1 0 pgm security bit 1 0 0 0* v pp 1 1 1 1 pgm security bit 2 0 0 0* v pp 1 1 0 0 notes: 1. `0' = valid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75v 0.25v. 3. v cc = 5v 10% during programming and verification. * ale/prog receives 25 programming pulses while v pp is held at 12.75v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. ? trademark phrase of intel corporation.
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 35 a0a7 0 1 1 46mhz +5v pgm data +12.75v 25 100 m s pulses to ground 0 1 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87C575 su00249 figure 34. programming configuration ale/prog: ale/prog: 1 0 1 0 25 pulses 100 m s+ 10 10 m s min su00018 figure 35. prog waveform a0a7 0 1 1 46mhz +5v pgm data 1 1 0 0 enable 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87C575 su00250 figure 36. program verification
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 36 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 37) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p1.0p1.7 p2.0p2.4 port 0 ale/prog ea /v pp p2.7 enable su00020 t ehsh * for programming verification see figure 34. for verification conditions see figure 36. figure 37. eprom programming and verification
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 37 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 38 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 39 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors product specification 80c575/83c575/ 87C575 80c51 8-bit microcontroller family 8k/256 otp/rom/romless, 4 comparator, failure detect circuitry, watchdog timer 1998 may 01 40 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03854
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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